1. Technical Field
The invention relates generally to voltage reference circuits, and more particularly to a stable voltage generator that is immune to variations in the supply voltage.
2. Background Art
Throughout the development of integrated circuit technology, various methods have been used to provide supply voltages on-chip. Originally, power supply busses were simply coupled to the various circuit elements directly. This led to problems due to power supply instabilities. Therefore various buffering methods (such as the use of decoupling capacitors) have been used to isolate the external power supply from the power inputs.
More recently, the need has developed for the ability to generate power supply voltages on-chip that are different from those available externally. One such example is in dynamic random access memories (DRAMs). As discussed in the above-mentioned copending U.S. patent application Ser. No. 07/810,000 by Galbi et al., it is necessary to generate a boost voltage so that the DRAM cells can be restored to a full "1" potential at the completion of a read cycle. By definition, such boost voltages exceed the high power supply (Vdd) available from the microprocessor. In order to provide a stable boost voltage, such systems have a particular need for stable input supplies that are immune to external power supply variations.
U.S. Pat. No. 4,451,744, "Monolithic Integrated Reference Voltage Source" (issued May 1984 to Adam and assigned to ITT Industries) discloses a voltage source that utilizes two cascaded, diode-connected FETs. A first FET has its source connected to Vdd and its drain connected to the output. A second FET has its source coupled to the output and its drain connected to ground. The gate of the first FET is connected to ground, and the gate of the second FET is connected to the source of the first FET. The first FET is a depletion type FET, and the second FET is an enhancement type FET. In combination, the difference in the diode drops produced by the difference in threshold voltage between the enhancement and depletion devices produces a stable output voltage. U.S. Pat. No. 4,814,686, "FET Reference Voltage Generator Which Is Impervious To Input Voltage Fluctuations," (issued March 1989 to Watanabe and assigned to Toshiba) discloses a voltage reference circuit in which a cascaded diode network provides an input voltage to another diode network, the two networks receiving different input currents, so as to provide a stable supply.
Other examples of voltage references that rely on diode differences to provide an output that is more immune to power supply variations include U.S. Pat. No. 4,064,448, "Band Gap Voltage Regulator Circuit Including A Merged Reference Voltage Source And Error Amplifier," (issued February 1977 and assigned to Fairchild); U.S. Pat. No. 4,317,054, "Bandgap Voltage Reference Employing Sub-Surface Current Using A Standard CMOS Process," (issued February 1982 and assigned to Mostek); U.S. Pat. No. 4,670,706, "Constand Voltage Generating Circuit," (issued June 1987 and assigned to Mitsubishi); U.S. Pat. No. 4,839,535, "MOS Bandgap Voltage Reference Circuit," (issued June 1989 and assigned to Motorola); and the article "Silicon Band-Gap Reference Voltage Generators Based On Dual Polysilicon MOS Transistors," IBM Technical Disclosure Bulletin, Vol. 2, No. 9B, February 1990, pp. 4-5.
Although most of the circuits disclosed above provide relatively stable supplies, they do so at the cost of high device counts and multiple current paths that result in higher power burn and poor Vdd excursion tolerance. Accordingly, a need has developed in the art for a relatively simple voltage reference circuit that has a minimum of current paths, and improved power supply excursion tolerance, and yet is insensitive to variations in external power supplies.